Building RTL Workloads for the Acceleration Stack for Intel® Xeon® CPU with FPGAs

The Acceleration Stack for Intel Xeon CPU with FPGAs is a robust collection of software, firmware, and tools intended to make it easier to develop and deploy Intel FPGAs for workload optimization in the data center. In this training, we will discuss how to develop an Accelerator Function Unit (AFU) for the FPGA using traditional RTL development and debug methods, and how to interact with it from the Acceleration Stack software using the Open Programmable Acceleration Engine (OPAE).

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