This training is part 4 of 4. The Partial Reconfiguration (PR) feature found in Intel® FPGA devices allows you to, at any time during normal operation, replace functional parts of your design with completely different logic while the rest of your design continues to operate normally. Combined with transceiver and PLL dynamic reconfiguration, and you have a complete solution for runtime functionality changes and design upgrades. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Intel Arria 10 GX development kit.